Process and structure for masking integrated capacitors of particular utility for ferroelectric memory integrated circuits

ABSTRACT

A method for fabricating integrated capacitors, of particular utility in forming a ferroelectric capacitor array for a ferroelectric memory integrated circuits, begins with provision of a substrate. The substrate is typically a partially-processed CMOS integrated circuit wafer coated with an adhesion layer. Upon the substrate is deposited a bottom electrode layer, typically of noble metal, a dielectric layer, typically doped PZT, and a top electrode layer, typically a noble metal oxide. Next is deposited a hardmask layer of strontium ruthenium oxide, followed by a photoresist layer. The photoresist layer is aligned, exposed, developed, and cured as known in the art of integrated circuit photolithography. The resulting stack is then dry etched to remove undesired portions of the hardmask layer, the top electrode layer, and the dielectric layer. A principle advantage of the process is that a single photomasking operation is sufficient to define the top electrode and dielectric layers.

RELATED APPLICATION

[0001] The present application is a divisional filing of co-pending U.S.patent application Ser. No. 09/797,394, filed Feb. 28, 2001, which ishereby incorporated by reference in its entirety.

FIELD OF THE INVENTION

[0002] The invention relates to the field of fabricating integratedcapacitors. In particular it relates to structure of, and methods forfabrication of, integrated capacitors as used in ferroelectric memoryintegrated circuits. The invention relates in particular to deposition,masking, and etching, of the dielectric and electrode layers offerroelectric capacitors in ferroelectric memory integrated circuits.

BACKGROUND OF THE INVENTION

[0003] Standard Dynamic Random Access Memory (DRAM) and Static RandomAccess Memory (SRAM) devices are considered volatile memory devicesbecause data stored therein is lost when power is lost. Nonvolatilememory devices are those that can retain data despite loss of power.

[0004] At present, there is a strong market for EEPROM (ElectricallyErasable, Programmable Read Only Memory), and Flash EEPROM nonvolatilememory devices. These devices tend to be slow to write, often havingwrite times on the order of milliseconds, while read times rangegenerally between one nanosecond and one microsecond. The greatdifference between read and write times, together with the block-erasecharacter of Flash EEPROM, complicates design of some systems. CMOS SRAMor DRAM with battery backup power for data retention can providesymmetrical, fast, read and write times in nonvolatile memory but isexpensive, requires presence of a battery, and limits system life orrequires eventual battery replacement.

[0005] It is known that Ferroelectric Random Access Memory (FRAM) is anonvolatile memory technology having potential for both read and writetimes below one microsecond. FRAM nonvolatile memory devices based onLead Zirconium Titanate (PZT) ferroelectric storage capacitors as memoryelements integrated with CMOS addressing, selection, and control logicare known in the art and are commercially available. PLZT is aLanthanum-doped form of PZT wherein some of the lead is replaced withLanthanum, for purposes of this patent the term PZT includes PLZT. It isknown that PZT may additionally be doped with strontium and calcium toimprove its ferroelectric dielectric properties. Ferroelectric storagecapacitors having a strontium bismuth tantalate (SBT) dielectric arealso known in the art. For purposes of this patent the termFerroelectric Dielectric includes both PZT and SBT materials.

[0006] It is expected that FRAM devices having smaller device geometriesand smaller ferroelectric storage capacitors than currently availabledevices will offer greater speed and storage density at lower cost.Producing such FRAM devices requires production of well-defined,uniform, high quality, ferroelectric storage capacitors integrated withCMOS addressing and control logic.

[0007] Ferroelectric storage capacitors of FRAM devices have a bottomelectrode interfacing with a ferroelectric layer, often PZT or SBT, thatserves as the ferroelectric dielectric. The ferroelectric layer istypically deposited on top of the bottom electrode, and a top electrodeis deposited on top of the ferroelectric layer. These layers are maskedand etched to define the size and location of each capacitor. Apassivation layer is formed over the resulting capacitors. This layer ismasked and etched to allow connection of each capacitor to othercomponents of each memory cell and to other components, such as CMOSaddressing, selection, and control logic of the integrated circuit.

[0008] A prior process for fabricating an array of ferroelectric storagecapacitors is described in U.S. Pat. No. 6,090,443, (the '443 patent)entitled “Multi-Layer approach for optimizing Ferroelectric FilmPerformance” and assigned to Ramtron International Corporation, ColoradoSprings, Colo., the disclosure of which is incorporated herein byreference. This process involves the following steps all performed afterdeposition of an adhesion layer onto a substrate, the substrate may be apartially processed CMOS integrated circuit wafer:

[0009] Deposition of a metallic bottom electrode layer.

[0010] Deposition of a PZT layer.

[0011] Annealing the deposited PZT.

[0012] Depositing a top electrode layer.

[0013] Once these layers are deposited, they must be patterned to forman array through at least one masking and etching sequence. Each maskingand etching sequence requires deposition of a photoresist over the arrayof partially processed capacitors, aligning the array with a photomask,exposing, developing, and curing the photoresist, and etching to removeundesired portions of the layers. The etching is controlled by remainingcured photoresist. Etching is typically performed with dry etchtechniques, such as plasma etching or ion milling.

[0014] It is known that typical dry etch techniques as commonly used inprocessing capacitor arrays cause damage to the cured photoresist usedto control etching. This damage may result in undercutting at edges ofresist opening. As cured photoresist layers are eaten away, this damagemay also result in undesired etching of those portions of the layersthat should remain to form the array.

[0015] Typically, fabricating such a capacitor array is performedthrough a sequence of two or more masking and etching sequences becauseexcessive damage to the photoresist occurs before the undesired portionsof the layers are adequately removed. It is known, however, thatrepeated masking and etching sequences are expensive and can result inundesirable edge profiles of remaining portions as a result ofmisalignment. The undesirable edge profiles may necessitate greaterspacing between capacitor array elements than may be otherwise possible.In particular, it is repeated photomasking operations that drive upcost.

[0016] It is also known that exposure of photoresist to dry etch causesrelease of an assortment of chemical compounds that contain carbon andhydrogen. It is also known that excessive exposure of ferroelectricdielectrics, such as PZT, to these compounds, including hydrogen, caninduce undesirable properties in the dielectrics. For this patent,induction of undesirable properties by these compounds is known asphotoresist byproduct poisoning of the dielectric. It is thereforedesirable to protect the dielectric layer from these chemical compoundsduring the etching process.

[0017] A hardmask is a layer of resistant material that is patternedwith photolithographic techniques as known in the art and used tocontrol circuit processing. The resistant material is a material that ismore stable than cured photoresist under at least some conditions, theseconditions may include etching, diffusing, or oxidizing conditions.Hardmask layers are occasionally used in the processing of integratedcircuits; although they are typically formed of nonconductive material.For example, standard CMOS processing uses a nonconductive siliconnitride hardmask layer to protect future diffused areas during fieldoxidation. U.S. Pat. No. 5,936,306 describes a process utilizing atitanium silicide layer as a conductive hard mask for controlling wetetch of titanium nitride. U.S. Pat. No. 5,998,258 discloses a processfor forming capacitors having a barium strontium titanate dielectricwherein a hardmask layer of titanium or tantalum nitride is used topattern a top electrode. U.S. Pat. No. 5,998,258 also suggests, incolumn 4, using a hardmask layer in fabrication of capacitors having PZTferroelectric dielectric and metallic top electrode.

[0018] Strontium ruthenium oxide, SrRuO₃ (SRO) is known to be aconductive metal oxide that has interesting magnetic properties. J. C.Jiang, X. Q. Pan and C. L. Chen discuss deposition of SRO films by laserablation in an article entitled: “Microstructure of Epitaxial SrRuO₃Thin Films on (001) SrTiO₃”.

SUMMARY OF THE INVENTION

[0019] This process involves the following steps all performed afterdeposition of an adhesion layer onto a substrate, the substrate may be apartially processed CMOS integrated circuit wafer:

[0020] Deposition of a metallic bottom electrode layer.

[0021] Deposition of a PZT dielectric layer.

[0022] Annealing the deposited dielectric.

[0023] Depositing a top electrode layer.

[0024] Depositing a strontium ruthenium oxide (SRO) hardmask layer overthe top electrode layer.

[0025] Depositing, exposing, developing, and curing a photoresist layerover the SRO layer.

[0026] Dry etching of the SRO and top electrode layers, while destroyingthe photoresist layer.

[0027] Dry etching of the dielectric as defined by openings etched inthe SRO and top electrode layers.

[0028] Depositing of a passivation and/or encapsulation layer.

[0029] Once these steps are performed, processing of the ferroelectricmemory integrated circuit and its capacitor array continues as known inthe art. Further processing includes: masking and etching of undesiredbottom electrode portions, masking and etching of vias in thepassivation layer to allow contact to electrodes of the capacitorsarray, as well as deposition, masking, and etching of circuitmetalization and insulator layers.

[0030] The great advantage of the process is that depositing, masking,exposing, and curing of only one photoresist layer is required to defineareas of the top electrode and ferroelectric dielectric layers.

[0031] A secondary advantage of the present process is that photoresistbyproduct poisoning of the dielectric is prevented because thephotoresist layer is removed before the PZT dielectric is exposed toetching plasma.

[0032] Since the process of the present invention can result in removalof the photoresist layer before the dielectric is exposed, lessphotoresist byproduct poisoning occurs than with standard processing.Further, it becomes possible to define the top electrode andferroelectric dielectric layers of the capacitor array with a singlemasking and etching sequence, thereby reducing costs.

[0033] The foregoing and other features, utilities and advantages of theinvention will be apparent from the following more particulardescription of a preferred embodiment of the invention as illustrated inthe accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0034]FIG. 1 is a cross section of an integrated capacitor afterdeposition of the bottom electrode, dielectric, top electrode, SROhardmask, and photoresist layers;

[0035]FIG. 2 is a flowchart of a representative process of the presentinvention;

[0036]FIG. 3, a cross section of the integrated capacitor of FIG. 1,after further steps of exposing, developing, and curing the photoresist,followed by dry etching to remove selected portions of the SRO hardmaskand thin or remove the photoresist;

[0037]FIG. 4, a cross section of the integrated capacitor of FIG. 2,after further dry etching to remove selected portions of the topelectrode layer and any remaining photoresist;

[0038]FIG. 5, a cross section of the integrated capacitor of FIG. 2,after further dry etching to remove selected portions of the dielectriclayer.

DETAILED DESCRIPTION

[0039] Initial processing of a Ferroelectric RAM integrated circuit isas known in the art of CMOS integrated circuit processing. Siliconwafers are processed as known through formation of wells andsource/drain diffused regions with deposition and masking of gates anddeposition of a dielectric oxide over the gates. These wafers becomesubstrates for formation of ferroelectric capacitor arrays. After theferroelectric capacitor arrays are formed, wafers are completed as knownin the art of CMOS integrated circuit processing, through masking andetching of contact and via holes, deposition, masking, and etching ofconductor layers, and deposition of intermetal dielectric and protectivepassivation layers.

[0040] With reference to FIGS. 1 and 2, formation of the ferroelectriccapacitor arrays begins with deposition of an adhesion layer onto asubstrate 10 (FIG. 1) comprising a partially-processed CMOS integratedcircuit wafer. The ferroelectric capacitors are typically grown on topof a silicon oxide or a chemical vapor deposition (“CVD”) layer of thewafer. On this oxide layer is sputtered a layer (not shown) of Titaniumfrom fifty to two hundred, preferably two hundred, angstroms thick. Thistitanium layer is oxidized at from 300 to 700 degrees C., with 700degrees C. preferred, for from ten minutes to one hour in oxygenatmosphere to form an adhesion layer 102 of titanium dioxide thatenhances adhesion, and thereby prevent delamination, of followinglayers. In those processes where platinum (Pt) is utilized, properorientation of the bottom electrode should be maintained.

[0041] On the oxidized titanium adhesion layer of the substrate 10 isdeposited 202 a conductive bottom electrode layer 104 from five hundredto two thousand five hundred angstroms thick, with about one thousandangstroms thickness preferred for optimum electrode quality. For optimumelectrode quality, and optimum quality of following PZT layers, thislayer comprises a noble metal, platinum preferred, and is deposited byDC sputtering with a substrate temperature of 450 to 600 degrees C. Forpurposes of this application, a noble metal is platinum, iridium,palladium, or another metal largely comprised of an element located inthe same region of the periodic table as platinum, iridium, andpalladium. Alternatively, some success has been achieved with bottomelectrodes fabricated of a conductive noble metal oxide, such as iridiumoxide or La_(0.5)Sr_(0.5)CoO₃ (“LSCO”). It is necessary that the meltingpoint of the bottom electrode be sufficiently high that it will not meltduring following high temperature processing steps, such as anneal stepsperformed at temperatures of five hundred to eight hundred degreesCelsius.

[0042] Next, one or more layers of lanthanum-doped PZT ferroelectricdielectric 14 is deposited 204. This may be a single layer 14 ofthickness about one thousand eight hundred angstroms of PZT, preferablymodified with calcium and strontium dopants to obtain desirableelectrical properties. Alternatively, a lead-rich, lanthanum doped, PZTferroelectric thin film of thickness about one hundred fifty angstromsmay be sputtered, preferably lanthanum doped and modified with calciumand strontium dopants. If used, this lead-rich layer is then topped witha further sputtered 206 bulk PZT layer 108 approximately one thousandsix hundred fifty angstroms thick, giving a total PZT thickness of aboutone thousand eight hundred angstroms. PZT deposition is preferably doneby RF sputtering on substrate having a temperature approximatelytwenty-five degrees C. PZT deposition may also be done by the sol-gelmethod as described on pages 400-401 of the Extended Abstracts of the1999 International Conference on Solid State Devices and Materials,Tokyo, 1999 or by an MOCVD method described in: “Common and UniqueAspects of Perovskite Thin Film CVD Processes” published in IntegratedFerroelectrics, in 1998 at Vol. 21, pages 273-289.

[0043] The PZT is next annealed 208 by rapid thermal annealing (RTA).This anneal is conducted in a low vacuum, or largely inert gasatmosphere, thereby having less oxygen than ambient air. It is desirablethat the atmosphere used for anneal contain an oxygen partial pressureno more than ten percent of one atmosphere. A mixture of approximately5% O₂ in argon at atmospheric pressure has been used. This step isreferenced herein as a first anneal, or a crystalization anneal.

[0044] For purposes of this application, the term noble gas is helium,argon, neon, or any other gases having similar properties and similarlysituated in the periodic table. The term inert gas comprises any gasthat does not significantly chemically react with the surface of anintegrated circuit under conditions of the process step in which it isused, and includes noble gas. The term low vacuum includes conditions ofgas mixtures comprising inert gas, air, and/or oxygen at total pressuresignificantly less than one atmosphere.

[0045] The partially annealed PZT is next capped by deposition 208 of asputtered amorphous iridium oxide (IrOx) conductive top electrode layer18 of thickness from one thousand to two thousand angstroms, with apreferred thickness of one thousand five hundred angstroms. Thiselectrode is deposited by DC sputtering on a substrate at roomtemperature. For purposes of this application, a noble metal oxide is anoxide of a noble metal as heretofore defined, including platinum andiridium oxides. While other conductive materials including noble metalsand noble metal oxides may serve as a top electrode, iridium oxide hasbeen found particularly effective as a top electrode layer.

[0046] After the top electrode layer 18 is deposited 208, a furtherconductive hardmask layer 20 of strontium ruthenium oxide (SrRuO₃)(SRO)approximately seven hundred fifty angstroms thick is deposited 210,preferably also by DC sputtering.

[0047] Once the SRO layer is deposited, a layer of photoresist 20 isdeposited 212. The photoresist is preferably about seven thousandangstroms thick, and is exposed to mercury-vapor I-line through asuitable mask using a reduction as known in the art of integratedcircuit manufacture, developed, and cured 214 in the manner known in theart.

[0048] After the photoresist is cured, the stack is placed in a plasmaetching machine. The dry etching machine is fed with a gas mixturecomprising four parts of Argon with one part of chlorine at one-halfPascal pressure for SRO 18 and top electrode 16 etch. This mixture isexcited to etch 216 undesired portions of the SRO layer as indicated inFIG. 3. During this phase of etching, the photoresist layer 20 issignificantly thinned or removed.

[0049] Etching under these conditions is continued to completely removethe photoresist layer 20 and remove undesired portions of the topelectrode 16 as illustrated in FIG. 4.

[0050] Once the top electrode 16 is etched, the gas mixture fed to theplasma etching machine is changed to two parts argon with one partchlorine at three tenths Pascal pressure; this mixture is excited asknown in the art of dry etching to remove undesired portions of the PZTlayer 14 as illustrated in FIG. 5. This second etching phase is a PZTetch 218.

[0051] Next a passivation and/or encapsulation layer 22 of PZT oraluminum oxide is deposited 220 over the capacitor structure, and theresulting capacitor structure is again annealed by rapid thermalannealing.

[0052] Processing continues 220 as known in the art to mask and etch thebottom electrode layer, and mask and etch contact holes in theencapsulation layer. Processing is also continued to deposit, mask, andetch the interconnect dielectric, passivation and metalization layerstypical of CMOS integrated circuits to interconnect the resultingferroelectric capacitors and other components of the circuit to producea Ferroelectric RAM integrated circuit.

[0053] Although a specific process comprising steps 200 through 222 hasbeen disclosed and described in detail, it should be recognized that aMOCVD PZT process may also be utilized to effectuate the presentinvention instead.

[0054] It is known that SRO etches more slowly in the dry etchconditions used than does IrOx and PZT. The thickness of SRO preferablyutilized varies the thickness of the top electrode and PZT layers,although it is generally in the range of from five hundred to onethousand angstroms thick for top electrode thicknesses as hereindisclosed. This thickness is chosen such that the photoresist layer iscompletely removed before the first etching step cuts through the topelectrode, such that the PZT layer is protected from direct exposure tothe gasses evolved as the photoresist is attacked by the etchingprocess. As a result, photoresist byproduct poisoning of the dielectricis prevented.

[0055] While the invention has been particularly shown and describedwith reference to a preferred embodiment thereof, it will be understoodby those skilled in the art that various other changes in the form anddetails may be made without departing from the spirit and scope of theinvention.

What is claimed is:
 1. An integrated capacitor comprising: a bottomelectrode layer, a dielectric layer disposed on the bottom electrodelayer, a top electrode layer disposed on the dielectric layer; and aconductive hardmask layer disposed on the top electrode layer.
 2. Theintegrated capacitor of claim 1, wherein the dielectric layer comprisesa ferroelectric dielectric material.
 3. The integrated capacitor ofclaim 2, wherein the conductive hardmask layer comprises strontiumruthenium oxide.
 4. The integrated capacitor of claim 3, wherein the topelectrode layer comprises a noble metal oxide.
 5. The integratedcapacitor of claim 4, wherein the bottom electrode layer comprises anoble metal. 6 The integrated capacitor of claim 5, wherein the bottomelectrode layer comprises platinum, the dielectric layer compriseslead-zirconium-titanate, and the top electrode layer comprises iridiumoxide.
 7. The integrated capacitor of claim 6, further comprising anadhesion layer and a passivation layer.